LLVM 22.0.0git
Classes | Typedefs | Enumerations | Variables
llvm::X86Disassembler Namespace Reference

Classes

struct  InstructionSpecifier
 The specification for how to extract and interpret a full instruction and its operands. More...
struct  InternalInstruction
 The x86 internal instruction, which is produced by the decoder. More...
struct  OperandSpecifier
 The specification for how to extract and interpret one operand. More...

Typedefs

typedef uint16_t InstrUID

Enumerations

enum  attributeBits {
  ATTR_NONE = 0x00 , ATTR_64BIT = 0x1 << 0 , ATTR_XS = 0x1 << 1 , ATTR_XD = 0x1 << 2 ,
  ATTR_REXW = 0x1 << 3 , ATTR_OPSIZE = 0x1 << 4 , ATTR_ADSIZE = 0x1 << 5 , ATTR_VEX = 0x1 << 6 ,
  ATTR_VEXL = 0x1 << 7 , ATTR_EVEX = 0x1 << 8 , ATTR_EVEXL2 = 0x1 << 9 , ATTR_EVEXK = 0x1 << 10 ,
  ATTR_EVEXKZ = 0x1 << 11 , ATTR_EVEXB = 0x1 << 12 , ATTR_REX2 = 0x1 << 13 , ATTR_EVEXNF = 0x1 << 14 ,
  ATTR_EVEXU = 0x1 << 15 , ATTR_max = 0x1 << 16
}
enum  InstructionContext { IC_max }
enum  OpcodeType {
  ONEBYTE = 0 , TWOBYTE = 1 , THREEBYTE_38 = 2 , THREEBYTE_3A = 3 ,
  XOP8_MAP = 4 , XOP9_MAP = 5 , XOPA_MAP = 6 , THREEDNOW_MAP = 7 ,
  MAP4 = 8 , MAP5 = 9 , MAP6 = 10 , MAP7 = 11
}
enum  ModRMDecisionType { MODRM_max }
enum  OperandEncoding { ENCODING_max }
enum  OperandType { TYPE_max }
enum  DisassemblerMode { MODE_16BIT , MODE_32BIT , MODE_64BIT }
 Decoding mode for the Intel disassembler. More...
enum  EABase { EA_BASE_NONE , EA_max }
 All possible values of the base field for effective-address computations, a.k.a. More...
enum  SIBIndex { SIB_INDEX_NONE , SIB_INDEX_max }
 All possible values of the SIB index field. More...
enum  SIBBase { SIB_BASE_NONE , SIB_BASE_max }
 All possible values of the SIB base field. More...
enum  EADisplacement { EA_DISP_NONE , EA_DISP_8 , EA_DISP_16 , EA_DISP_32 }
 Possible displacement types for effective-address computations. More...
enum  Reg { MODRM_REG_max }
 All possible values of the reg field in the ModR/M byte. More...
enum  SegmentOverride {
  SEG_OVERRIDE_NONE , SEG_OVERRIDE_CS , SEG_OVERRIDE_SS , SEG_OVERRIDE_DS ,
  SEG_OVERRIDE_ES , SEG_OVERRIDE_FS , SEG_OVERRIDE_GS , SEG_OVERRIDE_max
}
 All possible segment overrides. More...
enum  VEXLeadingOpcodeByte {
  VEX_LOB_0F = 0x1 , VEX_LOB_0F38 = 0x2 , VEX_LOB_0F3A = 0x3 , VEX_LOB_MAP4 = 0x4 ,
  VEX_LOB_MAP5 = 0x5 , VEX_LOB_MAP6 = 0x6 , VEX_LOB_MAP7 = 0x7
}
 Possible values for the VEX.m-mmmm field. More...
enum  XOPMapSelect { XOP_MAP_SELECT_8 = 0x8 , XOP_MAP_SELECT_9 = 0x9 , XOP_MAP_SELECT_A = 0xA }
enum  VEXPrefixCode { VEX_PREFIX_NONE = 0x0 , VEX_PREFIX_66 = 0x1 , VEX_PREFIX_F3 = 0x2 , VEX_PREFIX_F2 = 0x3 }
 Possible values for the VEX.pp/EVEX.pp field. More...
enum  VectorExtensionType {
  TYPE_NO_VEX_XOP = 0x0 , TYPE_VEX_2B = 0x1 , TYPE_VEX_3B = 0x2 , TYPE_EVEX = 0x3 ,
  TYPE_XOP = 0x4
}

Variables

static const unsigned X86_MAX_OPERANDS = 6

Typedef Documentation

◆ InstrUID

typedef uint16_t llvm::X86Disassembler::InstrUID

Definition at line 394 of file X86DisassemblerDecoderCommon.h.

Enumeration Type Documentation

◆ attributeBits

enum llvm::X86Disassembler::attributeBits
Enumerator
ATTR_NONE 
ATTR_64BIT 
ATTR_XS 
ATTR_XD 
ATTR_REXW 
ATTR_OPSIZE 
ATTR_ADSIZE 
ATTR_VEX 
ATTR_VEXL 
ATTR_EVEX 
ATTR_EVEXL2 
ATTR_EVEXK 
ATTR_EVEXKZ 
ATTR_EVEXB 
ATTR_REX2 
ATTR_EVEXNF 
ATTR_EVEXU 
ATTR_max 

Definition at line 56 of file X86DisassemblerDecoderCommon.h.

◆ DisassemblerMode

enum llvm::X86Disassembler::DisassemblerMode

Decoding mode for the Intel disassembler.

16-bit, 32-bit, and 64-bit mode are supported, and represent real mode, IA-32e, and IA-32e in 64-bit mode, respectively.

Enumerator
MODE_16BIT 
MODE_32BIT 
MODE_64BIT 

Definition at line 541 of file X86DisassemblerDecoderCommon.h.

◆ EABase

enum llvm::X86Disassembler::EABase

All possible values of the base field for effective-address computations, a.k.a.

the Mod and R/M fields of the ModR/M byte. We distinguish between bases (EA_BASE_*) and registers that just happen to be referred to when Mod == 0b11 (EA_REG_*).

Enumerator
EA_BASE_NONE 
EA_max 

Definition at line 568 of file X86DisassemblerDecoder.h.

◆ EADisplacement

enum llvm::X86Disassembler::EADisplacement

Possible displacement types for effective-address computations.

Enumerator
EA_DISP_NONE 
EA_DISP_8 
EA_DISP_16 
EA_DISP_32 

Definition at line 610 of file X86DisassemblerDecoder.h.

◆ InstructionContext

enum llvm::X86Disassembler::InstructionContext
Enumerator
IC_max 

Definition at line 367 of file X86DisassemblerDecoderCommon.h.

◆ ModRMDecisionType

enum llvm::X86Disassembler::ModRMDecisionType
Enumerator
MODRM_max 

Definition at line 420 of file X86DisassemblerDecoderCommon.h.

◆ OpcodeType

enum llvm::X86Disassembler::OpcodeType
Enumerator
ONEBYTE 
TWOBYTE 
THREEBYTE_38 
THREEBYTE_3A 
XOP8_MAP 
XOP9_MAP 
XOPA_MAP 
THREEDNOW_MAP 
MAP4 
MAP5 
MAP6 
MAP7 

Definition at line 372 of file X86DisassemblerDecoderCommon.h.

◆ OperandEncoding

enum llvm::X86Disassembler::OperandEncoding
Enumerator
ENCODING_max 

Definition at line 485 of file X86DisassemblerDecoderCommon.h.

◆ OperandType

enum llvm::X86Disassembler::OperandType
Enumerator
TYPE_max 

Definition at line 527 of file X86DisassemblerDecoderCommon.h.

◆ Reg

enum llvm::X86Disassembler::Reg

All possible values of the reg field in the ModR/M byte.

Enumerator
MODRM_REG_max 

Definition at line 614 of file X86DisassemblerDecoder.h.

◆ SegmentOverride

enum llvm::X86Disassembler::SegmentOverride

All possible segment overrides.

Enumerator
SEG_OVERRIDE_NONE 
SEG_OVERRIDE_CS 
SEG_OVERRIDE_SS 
SEG_OVERRIDE_DS 
SEG_OVERRIDE_ES 
SEG_OVERRIDE_FS 
SEG_OVERRIDE_GS 
SEG_OVERRIDE_max 

Definition at line 623 of file X86DisassemblerDecoder.h.

◆ SIBBase

enum llvm::X86Disassembler::SIBBase

All possible values of the SIB base field.

Enumerator
SIB_BASE_NONE 
SIB_BASE_max 

Definition at line 599 of file X86DisassemblerDecoder.h.

◆ SIBIndex

enum llvm::X86Disassembler::SIBIndex

All possible values of the SIB index field.

borrows entries from ALL_EA_BASES with the special case that sib is synonymous with NONE. Vector SIB: index can be XMM or YMM.

Enumerator
SIB_INDEX_NONE 
SIB_INDEX_max 

Definition at line 585 of file X86DisassemblerDecoder.h.

◆ VectorExtensionType

enum llvm::X86Disassembler::VectorExtensionType
Enumerator
TYPE_NO_VEX_XOP 
TYPE_VEX_2B 
TYPE_VEX_3B 
TYPE_EVEX 
TYPE_XOP 

Definition at line 659 of file X86DisassemblerDecoder.h.

◆ VEXLeadingOpcodeByte

enum llvm::X86Disassembler::VEXLeadingOpcodeByte

Possible values for the VEX.m-mmmm field.

Enumerator
VEX_LOB_0F 
VEX_LOB_0F38 
VEX_LOB_0F3A 
VEX_LOB_MAP4 
VEX_LOB_MAP5 
VEX_LOB_MAP6 
VEX_LOB_MAP7 

Definition at line 635 of file X86DisassemblerDecoder.h.

◆ VEXPrefixCode

enum llvm::X86Disassembler::VEXPrefixCode

Possible values for the VEX.pp/EVEX.pp field.

Enumerator
VEX_PREFIX_NONE 
VEX_PREFIX_66 
VEX_PREFIX_F3 
VEX_PREFIX_F2 

Definition at line 652 of file X86DisassemblerDecoder.h.

◆ XOPMapSelect

enum llvm::X86Disassembler::XOPMapSelect
Enumerator
XOP_MAP_SELECT_8 
XOP_MAP_SELECT_9 
XOP_MAP_SELECT_A 

Definition at line 645 of file X86DisassemblerDecoder.h.

Variable Documentation

◆ X86_MAX_OPERANDS

const unsigned llvm::X86Disassembler::X86_MAX_OPERANDS = 6
static

Definition at line 536 of file X86DisassemblerDecoderCommon.h.

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