#include "Target/AMDGPU/AMDGPUCombinerHelper.h"

Inheritance diagram for llvm::AMDGPUCombinerHelper:

Public Member Functions
	AMDGPUCombinerHelper (GISelChangeObserver &Observer, MachineIRBuilder &B, bool IsPreLegalize, GISelValueTracking VT, MachineDominatorTree MDT, const LegalizerInfo *LI, const GCNSubtarget &STI)
bool	matchFoldableFneg (MachineInstr &MI, MachineInstr *&MatchInfo) const
void	applyFoldableFneg (MachineInstr &MI, MachineInstr *&MatchInfo) const
bool	matchExpandPromotedF16FMed3 (MachineInstr &MI, Register Src0, Register Src1, Register Src2) const
void	applyExpandPromotedF16FMed3 (MachineInstr &MI, Register Src0, Register Src1, Register Src2) const
bool	matchCombineFmulWithSelectToFldexp (MachineInstr &MI, MachineInstr &Sel, std::function< void(MachineIRBuilder &)> &MatchInfo) const
bool	matchConstantIs32BitMask (Register Reg) const
	CombinerHelper (GISelChangeObserver &Observer, MachineIRBuilder &B, bool IsPreLegalize, GISelValueTracking VT=nullptr, MachineDominatorTree MDT=nullptr, const LegalizerInfo *LI=nullptr)
Public Member Functions inherited from llvm::CombinerHelper
	CombinerHelper (GISelChangeObserver &Observer, MachineIRBuilder &B, bool IsPreLegalize, GISelValueTracking VT=nullptr, MachineDominatorTree MDT=nullptr, const LegalizerInfo *LI=nullptr)
GISelValueTracking *	getValueTracking () const
MachineIRBuilder &	getBuilder () const
const TargetLowering &	getTargetLowering () const
const MachineFunction &	getMachineFunction () const
const DataLayout &	getDataLayout () const
LLVMContext &	getContext () const
bool	isPreLegalize () const
bool	isLegal (const LegalityQuery &Query) const
bool	isLegalOrBeforeLegalizer (const LegalityQuery &Query) const
bool	isLegalOrHasWidenScalar (const LegalityQuery &Query) const
bool	isConstantLegalOrBeforeLegalizer (const LLT Ty) const
void	replaceRegWith (MachineRegisterInfo &MRI, Register FromReg, Register ToReg) const
	MachineRegisterInfo::replaceRegWith() and inform the observer of the changes.
void	replaceRegOpWith (MachineRegisterInfo &MRI, MachineOperand &FromRegOp, Register ToReg) const
	Replace a single register operand with a new register and inform the observer of the changes.
void	replaceOpcodeWith (MachineInstr &FromMI, unsigned ToOpcode) const
	Replace the opcode in instruction with a new opcode and inform the observer of the changes.
const RegisterBank *	getRegBank (Register Reg) const
	Get the register bank of `Reg`.
void	setRegBank (Register Reg, const RegisterBank *RegBank) const
	Set the register bank of `Reg`.
bool	tryCombineCopy (MachineInstr &MI) const
	If `MI` is COPY, try to combine it.
bool	matchCombineCopy (MachineInstr &MI) const
void	applyCombineCopy (MachineInstr &MI) const
bool	isPredecessor (const MachineInstr &DefMI, const MachineInstr &UseMI) const
	Returns true if `DefMI` precedes `UseMI` or they are the same instruction.
bool	dominates (const MachineInstr &DefMI, const MachineInstr &UseMI) const
	Returns true if `DefMI` dominates `UseMI`.
bool	tryCombineExtendingLoads (MachineInstr &MI) const
	If `MI` is extend that consumes the result of a load, try to combine it.
bool	matchCombineExtendingLoads (MachineInstr &MI, PreferredTuple &MatchInfo) const
void	applyCombineExtendingLoads (MachineInstr &MI, PreferredTuple &MatchInfo) const
bool	matchCombineLoadWithAndMask (MachineInstr &MI, BuildFnTy &MatchInfo) const
	Match (and (load x), mask) -> zextload x.
bool	matchCombineExtractedVectorLoad (MachineInstr &MI, BuildFnTy &MatchInfo) const
	Combine a G_EXTRACT_VECTOR_ELT of a load into a narrowed load.
bool	matchCombineIndexedLoadStore (MachineInstr &MI, IndexedLoadStoreMatchInfo &MatchInfo) const
void	applyCombineIndexedLoadStore (MachineInstr &MI, IndexedLoadStoreMatchInfo &MatchInfo) const
bool	matchSextTruncSextLoad (MachineInstr &MI) const
void	applySextTruncSextLoad (MachineInstr &MI) const
bool	matchSextInRegOfLoad (MachineInstr &MI, std::tuple< Register, unsigned > &MatchInfo) const
	Match sext_inreg(load p), imm -> sextload p.
void	applySextInRegOfLoad (MachineInstr &MI, std::tuple< Register, unsigned > &MatchInfo) const
bool	matchCombineDivRem (MachineInstr &MI, MachineInstr *&OtherMI) const
	Try to combine G_[SU]DIV and G_[SU]REM into a single G_[SU]DIVREM when their source operands are identical.
void	applyCombineDivRem (MachineInstr &MI, MachineInstr *&OtherMI) const
bool	matchOptBrCondByInvertingCond (MachineInstr &MI, MachineInstr *&BrCond) const
	If a brcond's true block is not the fallthrough, make it so by inverting the condition and swapping operands.
void	applyOptBrCondByInvertingCond (MachineInstr &MI, MachineInstr *&BrCond) const
bool	matchCombineConcatVectors (MachineInstr &MI, SmallVector< Register > &Ops) const
	If `MI` is G_CONCAT_VECTORS, try to combine it.
void	applyCombineConcatVectors (MachineInstr &MI, SmallVector< Register > &Ops) const
	Replace `MI` with a flattened build_vector with `Ops` or an implicit_def if `Ops` is empty.
bool	matchCombineShuffleConcat (MachineInstr &MI, SmallVector< Register > &Ops) const
void	applyCombineShuffleConcat (MachineInstr &MI, SmallVector< Register > &Ops) const
	Replace `MI` with a flattened build_vector with `Ops` or an implicit_def if `Ops` is empty.
void	applyCombineShuffleToBuildVector (MachineInstr &MI) const
	Replace `MI` with a build_vector.
bool	tryCombineShuffleVector (MachineInstr &MI) const
	Try to combine G_SHUFFLE_VECTOR into G_CONCAT_VECTORS.
bool	matchCombineShuffleVector (MachineInstr &MI, SmallVectorImpl< Register > &Ops) const
	Check if the G_SHUFFLE_VECTOR `MI` can be replaced by a concat_vectors.
void	applyCombineShuffleVector (MachineInstr &MI, ArrayRef< Register > Ops) const
	Replace `MI` with a concat_vectors with `Ops`.
bool	tryCombineMemCpyFamily (MachineInstr &MI, unsigned MaxLen=0) const
	Optimize memcpy intrinsics et al, e.g.
bool	matchPtrAddImmedChain (MachineInstr &MI, PtrAddChain &MatchInfo) const
void	applyPtrAddImmedChain (MachineInstr &MI, PtrAddChain &MatchInfo) const
bool	matchShiftImmedChain (MachineInstr &MI, RegisterImmPair &MatchInfo) const
	Fold (shift (shift base, x), y) -> (shift base (x+y))
void	applyShiftImmedChain (MachineInstr &MI, RegisterImmPair &MatchInfo) const
bool	matchShiftOfShiftedLogic (MachineInstr &MI, ShiftOfShiftedLogic &MatchInfo) const
	If we have a shift-by-constant of a bitwise logic op that itself has a shift-by-constant operand with identical opcode, we may be able to convert that into 2 independent shifts followed by the logic op.
void	applyShiftOfShiftedLogic (MachineInstr &MI, ShiftOfShiftedLogic &MatchInfo) const
bool	matchCommuteShift (MachineInstr &MI, BuildFnTy &MatchInfo) const
bool	matchLshrOfTruncOfLshr (MachineInstr &MI, LshrOfTruncOfLshr &MatchInfo, MachineInstr &ShiftMI) const
	Fold (lshr (trunc (lshr x, C1)), C2) -> trunc (shift x, (C1 + C2))
void	applyLshrOfTruncOfLshr (MachineInstr &MI, LshrOfTruncOfLshr &MatchInfo) const
bool	matchCombineMulToShl (MachineInstr &MI, unsigned &ShiftVal) const
	Transform a multiply by a power-of-2 value to a left shift.
void	applyCombineMulToShl (MachineInstr &MI, unsigned &ShiftVal) const
bool	matchCombineSubToAdd (MachineInstr &MI, BuildFnTy &MatchInfo) const
bool	matchCombineShlOfExtend (MachineInstr &MI, RegisterImmPair &MatchData) const
void	applyCombineShlOfExtend (MachineInstr &MI, const RegisterImmPair &MatchData) const
bool	matchCombineMergeUnmerge (MachineInstr &MI, Register &MatchInfo) const
	Fold away a merge of an unmerge of the corresponding values.
bool	matchCombineShiftToUnmerge (MachineInstr &MI, unsigned TargetShiftSize, unsigned &ShiftVal) const
	Reduce a shift by a constant to an unmerge and a shift on a half sized type.
void	applyCombineShiftToUnmerge (MachineInstr &MI, const unsigned &ShiftVal) const
bool	tryCombineShiftToUnmerge (MachineInstr &MI, unsigned TargetShiftAmount) const
bool	matchCombineUnmergeMergeToPlainValues (MachineInstr &MI, SmallVectorImpl< Register > &Operands) const
	Transform <ty,...> G_UNMERGE(G_MERGE ty X, Y, Z) -> ty X, Y, Z.
void	applyCombineUnmergeMergeToPlainValues (MachineInstr &MI, SmallVectorImpl< Register > &Operands) const
bool	matchCombineUnmergeConstant (MachineInstr &MI, SmallVectorImpl< APInt > &Csts) const
	Transform G_UNMERGE Constant -> Constant1, Constant2, ...
void	applyCombineUnmergeConstant (MachineInstr &MI, SmallVectorImpl< APInt > &Csts) const
bool	matchCombineUnmergeUndef (MachineInstr &MI, std::function< void(MachineIRBuilder &)> &MatchInfo) const
	Transform G_UNMERGE G_IMPLICIT_DEF -> G_IMPLICIT_DEF, G_IMPLICIT_DEF, ...
bool	matchCombineUnmergeWithDeadLanesToTrunc (MachineInstr &MI) const
	Transform X, Y<dead> = G_UNMERGE Z -> X = G_TRUNC Z.
void	applyCombineUnmergeWithDeadLanesToTrunc (MachineInstr &MI) const
bool	matchCombineUnmergeZExtToZExt (MachineInstr &MI) const
	Transform X, Y = G_UNMERGE(G_ZEXT(Z)) -> X = G_ZEXT(Z); Y = G_CONSTANT 0.
void	applyCombineUnmergeZExtToZExt (MachineInstr &MI) const
void	applyCombineConstantFoldFpUnary (MachineInstr &MI, const ConstantFP *Cst) const
	Transform fp_instr(cst) to constant result of the fp operation.
bool	matchCombineI2PToP2I (MachineInstr &MI, Register &Reg) const
	Transform IntToPtr(PtrToInt(x)) to x if cast is in the same address space.
void	applyCombineI2PToP2I (MachineInstr &MI, Register &Reg) const
void	applyCombineP2IToI2P (MachineInstr &MI, Register &Reg) const
	Transform PtrToInt(IntToPtr(x)) to x.
bool	matchCombineAddP2IToPtrAdd (MachineInstr &MI, std::pair< Register, bool > &PtrRegAndCommute) const
	Transform G_ADD (G_PTRTOINT x), y -> G_PTRTOINT (G_PTR_ADD x, y) Transform G_ADD y, (G_PTRTOINT x) -> G_PTRTOINT (G_PTR_ADD x, y)
void	applyCombineAddP2IToPtrAdd (MachineInstr &MI, std::pair< Register, bool > &PtrRegAndCommute) const
bool	matchCombineConstPtrAddToI2P (MachineInstr &MI, APInt &NewCst) const
void	applyCombineConstPtrAddToI2P (MachineInstr &MI, APInt &NewCst) const
bool	matchCombineAnyExtTrunc (MachineInstr &MI, Register &Reg) const
	Transform anyext(trunc(x)) to x.
bool	matchCombineZextTrunc (MachineInstr &MI, Register &Reg) const
	Transform zext(trunc(x)) to x.
bool	matchCombineTruncOfShift (MachineInstr &MI, std::pair< MachineInstr *, LLT > &MatchInfo) const
	Transform trunc (shl x, K) to shl (trunc x), K if K < VT.getScalarSizeInBits().
void	applyCombineTruncOfShift (MachineInstr &MI, std::pair< MachineInstr *, LLT > &MatchInfo) const
bool	matchAnyExplicitUseIsUndef (MachineInstr &MI) const
	Return true if any explicit use operand on `MI` is defined by a G_IMPLICIT_DEF.
bool	matchAllExplicitUsesAreUndef (MachineInstr &MI) const
	Return true if all register explicit use operands on `MI` are defined by a G_IMPLICIT_DEF.
bool	matchUndefShuffleVectorMask (MachineInstr &MI) const
	Return true if a G_SHUFFLE_VECTOR instruction `MI` has an undef mask.
bool	matchUndefStore (MachineInstr &MI) const
	Return true if a G_STORE instruction `MI` is storing an undef value.
bool	matchUndefSelectCmp (MachineInstr &MI) const
	Return true if a G_SELECT instruction `MI` has an undef comparison.
bool	matchInsertExtractVecEltOutOfBounds (MachineInstr &MI) const
	Return true if a G_{EXTRACT,INSERT}_VECTOR_ELT has an out of range index.
bool	matchConstantSelectCmp (MachineInstr &MI, unsigned &OpIdx) const
	Return true if a G_SELECT instruction `MI` has a constant comparison.
void	replaceInstWithFConstant (MachineInstr &MI, double C) const
	Replace an instruction with a G_FCONSTANT with value `C`.
void	replaceInstWithFConstant (MachineInstr &MI, ConstantFP *CFP) const
	Replace an instruction with an G_FCONSTANT with value `CFP`.
void	replaceInstWithConstant (MachineInstr &MI, int64_t C) const
	Replace an instruction with a G_CONSTANT with value `C`.
void	replaceInstWithConstant (MachineInstr &MI, APInt C) const
	Replace an instruction with a G_CONSTANT with value `C`.
void	replaceInstWithUndef (MachineInstr &MI) const
	Replace an instruction with a G_IMPLICIT_DEF.
void	replaceSingleDefInstWithOperand (MachineInstr &MI, unsigned OpIdx) const
	Delete `MI` and replace all of its uses with its `OpIdx-th` operand.
void	replaceSingleDefInstWithReg (MachineInstr &MI, Register Replacement) const
	Delete `MI` and replace all of its uses with `Replacement`.
void	applyFunnelShiftConstantModulo (MachineInstr &MI) const
	Replaces the shift amount in `MI` with ShiftAmt % BW.
bool	matchEqualDefs (const MachineOperand &MOP1, const MachineOperand &MOP2) const
	Return true if `MOP1` and `MOP2` are register operands are defined by equivalent instructions.
bool	matchConstantOp (const MachineOperand &MOP, int64_t C) const
	Return true if `MOP` is defined by a G_CONSTANT or splat with a value equal to `C`.
bool	matchConstantFPOp (const MachineOperand &MOP, double C) const
	Return true if `MOP` is defined by a G_FCONSTANT or splat with a value exactly equal to `C`.
bool	matchConstantLargerBitWidth (MachineInstr &MI, unsigned ConstIdx) const
	Checks if constant at `ConstIdx` is larger than `MI` 's bitwidth.
bool	matchSelectSameVal (MachineInstr &MI) const
	Optimize (cond ? x : x) -> x.
bool	matchBinOpSameVal (MachineInstr &MI) const
	Optimize (x op x) -> x.
bool	matchOperandIsZero (MachineInstr &MI, unsigned OpIdx) const
	Check if operand `OpIdx` is zero.
bool	matchOperandIsUndef (MachineInstr &MI, unsigned OpIdx) const
	Check if operand `OpIdx` is undef.
bool	matchOperandIsKnownToBeAPowerOfTwo (MachineInstr &MI, unsigned OpIdx) const
	Check if operand `OpIdx` is known to be a power of 2.
void	eraseInst (MachineInstr &MI) const
	Erase `MI`.
bool	matchSimplifyAddToSub (MachineInstr &MI, std::tuple< Register, Register > &MatchInfo) const
	Return true if MI is a G_ADD which can be simplified to a G_SUB.
void	applySimplifyAddToSub (MachineInstr &MI, std::tuple< Register, Register > &MatchInfo) const
bool	matchHoistLogicOpWithSameOpcodeHands (MachineInstr &MI, InstructionStepsMatchInfo &MatchInfo) const
	Match (logic_op (op x...), (op y...)) -> (op (logic_op x, y))
void	applyBuildInstructionSteps (MachineInstr &MI, InstructionStepsMatchInfo &MatchInfo) const
	Replace `MI` with a series of instructions described in `MatchInfo`.
bool	matchAshrShlToSextInreg (MachineInstr &MI, std::tuple< Register, int64_t > &MatchInfo) const
	Match ashr (shl x, C), C -> sext_inreg (C)
void	applyAshShlToSextInreg (MachineInstr &MI, std::tuple< Register, int64_t > &MatchInfo) const
bool	matchOverlappingAnd (MachineInstr &MI, BuildFnTy &MatchInfo) const
	Fold and(and(x, C1), C2) -> C1&C2 ? and(x, C1&C2) : 0.
bool	matchRedundantAnd (MachineInstr &MI, Register &Replacement) const
bool	matchRedundantOr (MachineInstr &MI, Register &Replacement) const
bool	matchRedundantSExtInReg (MachineInstr &MI) const
bool	matchNotCmp (MachineInstr &MI, SmallVectorImpl< Register > &RegsToNegate) const
	Combine inverting a result of a compare into the opposite cond code.
void	applyNotCmp (MachineInstr &MI, SmallVectorImpl< Register > &RegsToNegate) const
bool	matchXorOfAndWithSameReg (MachineInstr &MI, std::pair< Register, Register > &MatchInfo) const
	Fold (xor (and x, y), y) -> (and (not x), y) {.
void	applyXorOfAndWithSameReg (MachineInstr &MI, std::pair< Register, Register > &MatchInfo) const
bool	matchPtrAddZero (MachineInstr &MI) const
	}
void	applyPtrAddZero (MachineInstr &MI) const
void	applySimplifyURemByPow2 (MachineInstr &MI) const
	Combine G_UREM x, (known power of 2) to an add and bitmasking.
bool	matchFoldBinOpIntoSelect (MachineInstr &MI, unsigned &SelectOpNo) const
	Push a binary operator through a select on constants.
void	applyFoldBinOpIntoSelect (MachineInstr &MI, const unsigned &SelectOpNo) const
	`SelectOperand` is the operand in binary operator `MI` that is the select to fold.
bool	matchCombineInsertVecElts (MachineInstr &MI, SmallVectorImpl< Register > &MatchInfo) const
void	applyCombineInsertVecElts (MachineInstr &MI, SmallVectorImpl< Register > &MatchInfo) const
bool	matchLoadOrCombine (MachineInstr &MI, BuildFnTy &MatchInfo) const
	Match expression trees of the form.
bool	matchExtendThroughPhis (MachineInstr &MI, MachineInstr *&ExtMI) const
void	applyExtendThroughPhis (MachineInstr &MI, MachineInstr *&ExtMI) const
bool	matchExtractVecEltBuildVec (MachineInstr &MI, Register &Reg) const
void	applyExtractVecEltBuildVec (MachineInstr &MI, Register &Reg) const
bool	matchExtractAllEltsFromBuildVector (MachineInstr &MI, SmallVectorImpl< std::pair< Register, MachineInstr * > > &MatchInfo) const
void	applyExtractAllEltsFromBuildVector (MachineInstr &MI, SmallVectorImpl< std::pair< Register, MachineInstr * > > &MatchInfo) const
void	applyBuildFn (MachineInstr &MI, BuildFnTy &MatchInfo) const
	Use a function which takes in a MachineIRBuilder to perform a combine.
void	applyBuildFnNoErase (MachineInstr &MI, BuildFnTy &MatchInfo) const
	Use a function which takes in a MachineIRBuilder to perform a combine.
bool	matchOrShiftToFunnelShift (MachineInstr &MI, bool AllowScalarConstants, BuildFnTy &MatchInfo) const
bool	matchFunnelShiftToRotate (MachineInstr &MI) const
	Match an FSHL or FSHR that can be combined to a ROTR or ROTL rotate.
void	applyFunnelShiftToRotate (MachineInstr &MI) const
bool	matchRotateOutOfRange (MachineInstr &MI) const
void	applyRotateOutOfRange (MachineInstr &MI) const
bool	matchUseVectorTruncate (MachineInstr &MI, Register &MatchInfo) const
void	applyUseVectorTruncate (MachineInstr &MI, Register &MatchInfo) const
bool	matchICmpToTrueFalseKnownBits (MachineInstr &MI, int64_t &MatchInfo) const
bool	matchICmpToLHSKnownBits (MachineInstr &MI, BuildFnTy &MatchInfo) const
bool	matchAndOrDisjointMask (MachineInstr &MI, BuildFnTy &MatchInfo) const
bool	matchBitfieldExtractFromSExtInReg (MachineInstr &MI, BuildFnTy &MatchInfo) const
	Form a G_SBFX from a G_SEXT_INREG fed by a right shift.
bool	matchBitfieldExtractFromAnd (MachineInstr &MI, BuildFnTy &MatchInfo) const
	Match: and (lshr x, cst), mask -> ubfx x, cst, width.
bool	matchBitfieldExtractFromShr (MachineInstr &MI, BuildFnTy &MatchInfo) const
	Match: shr (shl x, n), k -> sbfx/ubfx x, pos, width.
bool	matchBitfieldExtractFromShrAnd (MachineInstr &MI, BuildFnTy &MatchInfo) const
	Match: shr (and x, n), k -> ubfx x, pos, width.
bool	matchReassocConstantInnerRHS (GPtrAdd &MI, MachineInstr *RHS, BuildFnTy &MatchInfo) const
bool	matchReassocFoldConstantsInSubTree (GPtrAdd &MI, MachineInstr LHS, MachineInstr RHS, BuildFnTy &MatchInfo) const
bool	matchReassocConstantInnerLHS (GPtrAdd &MI, MachineInstr LHS, MachineInstr RHS, BuildFnTy &MatchInfo) const
bool	matchReassocPtrAdd (MachineInstr &MI, BuildFnTy &MatchInfo) const
	Reassociate pointer calculations with G_ADD involved, to allow better addressing mode usage.
bool	tryReassocBinOp (unsigned Opc, Register DstReg, Register Op0, Register Op1, BuildFnTy &MatchInfo) const
	Try to reassociate to reassociate operands of a commutative binop.
bool	matchReassocCommBinOp (MachineInstr &MI, BuildFnTy &MatchInfo) const
	Reassociate commutative binary operations like G_ADD.
bool	matchConstantFoldCastOp (MachineInstr &MI, APInt &MatchInfo) const
	Do constant folding when opportunities are exposed after MIR building.
bool	matchConstantFoldBinOp (MachineInstr &MI, APInt &MatchInfo) const
	Do constant folding when opportunities are exposed after MIR building.
bool	matchConstantFoldFPBinOp (MachineInstr &MI, ConstantFP *&MatchInfo) const
	Do constant FP folding when opportunities are exposed after MIR building.
bool	matchConstantFoldFMA (MachineInstr &MI, ConstantFP *&MatchInfo) const
	Constant fold G_FMA/G_FMAD.
bool	matchNarrowBinopFeedingAnd (MachineInstr &MI, BuildFnTy &MatchInfo) const
MachineInstr *	buildUDivOrURemUsingMul (MachineInstr &MI) const
	Given an G_UDIV `MI` or G_UREM `MI` expressing a divide by constant, return an expression that implements it by multiplying by a magic number.
bool	matchUDivOrURemByConst (MachineInstr &MI) const
	Combine G_UDIV or G_UREM by constant into a multiply by magic constant.
void	applyUDivOrURemByConst (MachineInstr &MI) const
MachineInstr *	buildSDivOrSRemUsingMul (MachineInstr &MI) const
	Given an G_SDIV `MI` or G_SREM `MI` expressing a signed divide by constant, return an expression that implements it by multiplying by a magic number.
bool	matchSDivOrSRemByConst (MachineInstr &MI) const
	Combine G_SDIV or G_SREM by constant into a multiply by magic constant.
void	applySDivOrSRemByConst (MachineInstr &MI) const
bool	matchDivByPow2 (MachineInstr &MI, bool IsSigned) const
	Given an G_SDIV `MI` expressing a signed divided by a pow2 constant, return expressions that implements it by shifting.
void	applySDivByPow2 (MachineInstr &MI) const
void	applyUDivByPow2 (MachineInstr &MI) const
	Given an G_UDIV `MI` expressing an unsigned divided by a pow2 constant, return expressions that implements it by shifting.
bool	matchUMulHToLShr (MachineInstr &MI) const
void	applyUMulHToLShr (MachineInstr &MI) const
bool	matchTruncSSatS (MachineInstr &MI, Register &MatchInfo) const
void	applyTruncSSatS (MachineInstr &MI, Register &MatchInfo) const
bool	matchTruncSSatU (MachineInstr &MI, Register &MatchInfo) const
void	applyTruncSSatU (MachineInstr &MI, Register &MatchInfo) const
bool	matchTruncUSatU (MachineInstr &MI, MachineInstr &MinMI) const
bool	matchTruncUSatUToFPTOUISat (MachineInstr &MI, MachineInstr &SrcMI) const
bool	tryCombine (MachineInstr &MI) const
	Try to transform `MI` by using all of the above combine functions.
bool	tryEmitMemcpyInline (MachineInstr &MI) const
	Emit loads and stores that perform the given memcpy.
bool	matchMulOBy2 (MachineInstr &MI, BuildFnTy &MatchInfo) const
	Match: (G_UMULO x, 2) -> (G_UADDO x, x) (G_SMULO x, 2) -> (G_SADDO x, x)
bool	matchMulOBy0 (MachineInstr &MI, BuildFnTy &MatchInfo) const
	Match: (G_*MULO x, 0) -> 0 + no carry out.
bool	matchAddEToAddO (MachineInstr &MI, BuildFnTy &MatchInfo) const
	Match: (G_ADDE x, y, 0) -> (G_ADDO x, y) (G_SUBE x, y, 0) -> (G_SUBO x, y)
bool	matchRedundantNegOperands (MachineInstr &MI, BuildFnTy &MatchInfo) const
	Transform (fadd x, fneg(y)) -> (fsub x, y) (fadd fneg(x), y) -> (fsub y, x) (fsub x, fneg(y)) -> (fadd x, y) (fmul fneg(x), fneg(y)) -> (fmul x, y) (fdiv fneg(x), fneg(y)) -> (fdiv x, y) (fmad fneg(x), fneg(y), z) -> (fmad x, y, z) (fma fneg(x), fneg(y), z) -> (fma x, y, z)
bool	matchFsubToFneg (MachineInstr &MI, Register &MatchInfo) const
void	applyFsubToFneg (MachineInstr &MI, Register &MatchInfo) const
bool	canCombineFMadOrFMA (MachineInstr &MI, bool &AllowFusionGlobally, bool &HasFMAD, bool &Aggressive, bool CanReassociate=false) const
bool	matchCombineFAddFMulToFMadOrFMA (MachineInstr &MI, BuildFnTy &MatchInfo) const
	Transform (fadd (fmul x, y), z) -> (fma x, y, z) (fadd (fmul x, y), z) -> (fmad x, y, z)
bool	matchCombineFAddFpExtFMulToFMadOrFMA (MachineInstr &MI, BuildFnTy &MatchInfo) const
	Transform (fadd (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), z) (fadd (fpext (fmul x, y)), z) -> (fmad (fpext x), (fpext y), z)
bool	matchCombineFAddFMAFMulToFMadOrFMA (MachineInstr &MI, BuildFnTy &MatchInfo) const
	Transform (fadd (fma x, y, (fmul u, v)), z) -> (fma x, y, (fma u, v, z)) (fadd (fmad x, y, (fmul u, v)), z) -> (fmad x, y, (fmad u, v, z))
bool	matchCombineFAddFpExtFMulToFMadOrFMAAggressive (MachineInstr &MI, BuildFnTy &MatchInfo) const
bool	matchCombineFSubFMulToFMadOrFMA (MachineInstr &MI, BuildFnTy &MatchInfo) const
	Transform (fsub (fmul x, y), z) -> (fma x, y, -z) (fsub (fmul x, y), z) -> (fmad x, y, -z)
bool	matchCombineFSubFNegFMulToFMadOrFMA (MachineInstr &MI, BuildFnTy &MatchInfo) const
	Transform (fsub (fneg (fmul, x, y)), z) -> (fma (fneg x), y, (fneg z)) (fsub (fneg (fmul, x, y)), z) -> (fmad (fneg x), y, (fneg z))
bool	matchCombineFSubFpExtFMulToFMadOrFMA (MachineInstr &MI, BuildFnTy &MatchInfo) const
	Transform (fsub (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), (fneg z)) (fsub (fpext (fmul x, y)), z) -> (fmad (fpext x), (fpext y), (fneg z))
bool	matchCombineFSubFpExtFNegFMulToFMadOrFMA (MachineInstr &MI, BuildFnTy &MatchInfo) const
	Transform (fsub (fpext (fneg (fmul x, y))), z) -> (fneg (fma (fpext x), (fpext y), z)) (fsub (fpext (fneg (fmul x, y))), z) -> (fneg (fmad (fpext x), (fpext y), z))
bool	matchCombineFMinMaxNaN (MachineInstr &MI, unsigned &Info) const
bool	matchRepeatedFPDivisor (MachineInstr &MI, SmallVector< MachineInstr * > &MatchInfo) const
void	applyRepeatedFPDivisor (SmallVector< MachineInstr * > &MatchInfo) const
bool	matchAddSubSameReg (MachineInstr &MI, Register &Src) const
	Transform G_ADD(x, G_SUB(y, x)) to y.
bool	matchBuildVectorIdentityFold (MachineInstr &MI, Register &MatchInfo) const
bool	matchTruncBuildVectorFold (MachineInstr &MI, Register &MatchInfo) const
bool	matchTruncLshrBuildVectorFold (MachineInstr &MI, Register &MatchInfo) const
bool	matchSubAddSameReg (MachineInstr &MI, BuildFnTy &MatchInfo) const
	Transform: (x + y) - y -> x (x + y) - x -> y x - (y + x) -> 0 - y x - (x + z) -> 0 - z.
bool	matchSimplifySelectToMinMax (MachineInstr &MI, BuildFnTy &MatchInfo) const
bool	matchRedundantBinOpInEquality (MachineInstr &MI, BuildFnTy &MatchInfo) const
	Transform: (X + Y) == X -> Y == 0 (X - Y) == X -> Y == 0 (X ^ Y) == X -> Y == 0 (X + Y) != X -> Y != 0 (X - Y) != X -> Y != 0 (X ^ Y) != X -> Y != 0.
bool	matchShiftsTooBig (MachineInstr &MI, std::optional< int64_t > &MatchInfo) const
	Match shifts greater or equal to the range (the bitwidth of the result datatype, or the effective bitwidth of the source value).
bool	matchCommuteConstantToRHS (MachineInstr &MI) const
	Match constant LHS ops that should be commuted.
bool	matchSextOfTrunc (const MachineOperand &MO, BuildFnTy &MatchInfo) const
	Combine sext of trunc.
bool	matchZextOfTrunc (const MachineOperand &MO, BuildFnTy &MatchInfo) const
	Combine zext of trunc.
bool	matchNonNegZext (const MachineOperand &MO, BuildFnTy &MatchInfo) const
	Combine zext nneg to sext.
bool	matchCommuteFPConstantToRHS (MachineInstr &MI) const
	Match constant LHS FP ops that should be commuted.
void	applyCommuteBinOpOperands (MachineInstr &MI) const
bool	matchSelectIMinMax (const MachineOperand &MO, BuildFnTy &MatchInfo) const
	Combine select to integer min/max.
bool	matchSimplifyNegMinMax (MachineInstr &MI, BuildFnTy &MatchInfo) const
	Tranform (neg (min/max x, (neg x))) into (max/min x, (neg x)).
bool	matchSelect (MachineInstr &MI, BuildFnTy &MatchInfo) const
	Combine selects.
bool	matchAnd (MachineInstr &MI, BuildFnTy &MatchInfo) const
	Combine ands.
bool	matchOr (MachineInstr &MI, BuildFnTy &MatchInfo) const
	Combine ors.
bool	matchNarrowBinop (const MachineInstr &TruncMI, const MachineInstr &BinopMI, BuildFnTy &MatchInfo) const
	trunc (binop X, C) --> binop (trunc X, trunc C).
bool	matchCastOfInteger (const MachineInstr &CastMI, APInt &MatchInfo) const
bool	matchAddOverflow (MachineInstr &MI, BuildFnTy &MatchInfo) const
	Combine addos.
bool	matchExtractVectorElement (MachineInstr &MI, BuildFnTy &MatchInfo) const
	Combine extract vector element.
bool	matchExtractVectorElementWithBuildVector (const MachineInstr &MI, const MachineInstr &MI2, BuildFnTy &MatchInfo) const
	Combine extract vector element with a build vector on the vector register.
bool	matchExtractVectorElementWithBuildVectorTrunc (const MachineOperand &MO, BuildFnTy &MatchInfo) const
	Combine extract vector element with a build vector trunc on the vector register.
bool	matchExtractVectorElementWithShuffleVector (const MachineInstr &MI, const MachineInstr &MI2, BuildFnTy &MatchInfo) const
	Combine extract vector element with a shuffle vector on the vector register.
bool	matchExtractVectorElementWithDifferentIndices (const MachineOperand &MO, BuildFnTy &MatchInfo) const
	Combine extract vector element with a insert vector element on the vector register and different indices.
bool	matchShuffleUndefRHS (MachineInstr &MI, BuildFnTy &MatchInfo) const
	Remove references to rhs if it is undef.
bool	matchShuffleDisjointMask (MachineInstr &MI, BuildFnTy &MatchInfo) const
	Turn shuffle a, b, mask -> shuffle undef, b, mask iff mask does not reference a.
void	applyBuildFnMO (const MachineOperand &MO, BuildFnTy &MatchInfo) const
	Use a function which takes in a MachineIRBuilder to perform a combine.
bool	matchFPowIExpansion (MachineInstr &MI, int64_t Exponent) const
	Match FPOWI if it's safe to extend it into a series of multiplications.
void	applyExpandFPowI (MachineInstr &MI, int64_t Exponent) const
	Expands FPOWI into a series of multiplications and a division if the exponent is negative.
bool	matchInsertVectorElementOOB (MachineInstr &MI, BuildFnTy &MatchInfo) const
	Combine insert vector element OOB.
bool	matchFreezeOfSingleMaybePoisonOperand (MachineInstr &MI, BuildFnTy &MatchInfo) const
bool	matchAddOfVScale (const MachineOperand &MO, BuildFnTy &MatchInfo) const
bool	matchMulOfVScale (const MachineOperand &MO, BuildFnTy &MatchInfo) const
bool	matchSubOfVScale (const MachineOperand &MO, BuildFnTy &MatchInfo) const
bool	matchShlOfVScale (const MachineOperand &MO, BuildFnTy &MatchInfo) const
bool	matchTruncateOfExt (const MachineInstr &Root, const MachineInstr &ExtMI, BuildFnTy &MatchInfo) const
	Transform trunc ([asz]ext x) to x or ([asz]ext x) or (trunc x).
bool	matchCastOfSelect (const MachineInstr &Cast, const MachineInstr &SelectMI, BuildFnTy &MatchInfo) const
bool	matchFoldAPlusC1MinusC2 (const MachineInstr &MI, BuildFnTy &MatchInfo) const
bool	matchFoldC2MinusAPlusC1 (const MachineInstr &MI, BuildFnTy &MatchInfo) const
bool	matchFoldAMinusC1MinusC2 (const MachineInstr &MI, BuildFnTy &MatchInfo) const
bool	matchFoldC1Minus2MinusC2 (const MachineInstr &MI, BuildFnTy &MatchInfo) const
bool	matchFoldAMinusC1PlusC2 (const MachineInstr &MI, BuildFnTy &MatchInfo) const
bool	matchExtOfExt (const MachineInstr &FirstMI, const MachineInstr &SecondMI, BuildFnTy &MatchInfo) const
bool	matchCastOfBuildVector (const MachineInstr &CastMI, const MachineInstr &BVMI, BuildFnTy &MatchInfo) const
bool	matchCanonicalizeICmp (const MachineInstr &MI, BuildFnTy &MatchInfo) const
bool	matchCanonicalizeFCmp (const MachineInstr &MI, BuildFnTy &MatchInfo) const
bool	matchUnmergeValuesAnyExtBuildVector (const MachineInstr &MI, BuildFnTy &MatchInfo) const
bool	matchMergeXAndUndef (const MachineInstr &MI, BuildFnTy &MatchInfo) const
bool	matchMergeXAndZero (const MachineInstr &MI, BuildFnTy &MatchInfo) const
bool	matchSuboCarryOut (const MachineInstr &MI, BuildFnTy &MatchInfo) const
bool	matchRedundantSextInReg (MachineInstr &Root, MachineInstr &Other, BuildFnTy &MatchInfo) const

Protected Attributes
const GCNSubtarget &	STI
const SIInstrInfo &	TII
Protected Attributes inherited from llvm::CombinerHelper
MachineIRBuilder &	Builder
MachineRegisterInfo &	MRI
GISelChangeObserver &	Observer
GISelValueTracking *	VT
MachineDominatorTree *	MDT
bool	IsPreLegalize
const LegalizerInfo *	LI
const RegisterBankInfo *	RBI
const TargetRegisterInfo *	TRI

Detailed Description

Definition at line 23 of file AMDGPUCombinerHelper.h.

Constructor & Destructor Documentation

◆ AMDGPUCombinerHelper()

AMDGPUCombinerHelper::AMDGPUCombinerHelper	(	GISelChangeObserver &	Observer,
		MachineIRBuilder &	B,
		bool	IsPreLegalize,
		GISelValueTracking *	VT,
		MachineDominatorTree *	MDT,
		const LegalizerInfo *	LI,
		const GCNSubtarget &	STI )

Definition at line 20 of file AMDGPUCombinerHelper.cpp.

References B(), CombinerHelper(), llvm::CombinerHelper::IsPreLegalize, llvm::CombinerHelper::LI, llvm::CombinerHelper::MDT, llvm::CombinerHelper::Observer, STI, TII, and llvm::CombinerHelper::VT.

Member Function Documentation

◆ applyExpandPromotedF16FMed3()

void AMDGPUCombinerHelper::applyExpandPromotedF16FMed3	(	MachineInstr &	MI,
		Register	Src0,
		Register	Src1,
		Register	Src2 ) const

Definition at line 438 of file AMDGPUCombinerHelper.cpp.

References llvm::CombinerHelper::Builder, MI, llvm::CombinerHelper::MRI, and llvm::LLT::scalar().

◆ applyFoldableFneg()

void AMDGPUCombinerHelper::applyFoldableFneg	(	MachineInstr &	MI,
		MachineInstr *&	MatchInfo ) const

◆ CombinerHelper()

CombinerHelper::CombinerHelper	(	GISelChangeObserver &	Observer,
		MachineIRBuilder &	B,
		bool	IsPreLegalize,
		GISelValueTracking *	VT = nullptr,
		MachineDominatorTree *	MDT = nullptr,
		const LegalizerInfo *	LI = nullptr )

Definition at line 127 of file CombinerHelper.cpp.

Referenced by AMDGPUCombinerHelper().

◆ matchCombineFmulWithSelectToFldexp()

bool AMDGPUCombinerHelper::matchCombineFmulWithSelectToFldexp	(	MachineInstr &	MI,
		MachineInstr &	Sel,
		std::function< void(MachineIRBuilder &)> &	MatchInfo ) const